1. Field of the Invention
The present invention relates to a semiconductor device having a function of DRAM interface, and particularly relates to a semiconductor device in which a DRAM circuit having the function of the DRAM interface and a logic circuit are mixed.
2. Description of the Related Art
Recently, as semiconductor devices with higher density and higher functions are achieved, a semiconductor device in which a DRAM circuit and other logic circuits are mixed on a single chip is desired as well as a general DRAM. In such a semiconductor device, a configuration for inputting/outputting data of a memory cell array and for transferring data between the DRAM circuit and the logic circuits is required. For example, when a logic circuit for performing high-speed operation such as image processing is mixed in the chip, high capacity data is input/output from/to a memory circuit so as to perform the high-speed operation. Thus, an input/output port having a wide bit width is required to be provided in the DRAM circuit and to be connected to the logic circuit.
FIG. 15 shows a specific example of the DRAM circuit including the input/output port having a wide bit width. In FIG. 15, a memory block 100 is configured in which there are provided a large number of memory cells MC formed at intersections between a plurality of word lines WL and a plurality of bit lines BL, a plurality of sense amplifiers SA for amplifying data of the memory cell MC for each bit line pair BP, and a plurality of select transistors ST inserted in each bit line BL in series. In the example of FIG. 15, the sense amplifiers SA and the select transistors ST are symmetrically arranged on both sides of the memory block 100. Further, a column decoder 101 selectively activates two select control lines 102 connected to gates of the select transistors ST on the both sides in response to an input column address.
In the DRAM circuit of FIG. 15, one ends of the select transistors ST on both sides of the bit lines BL are defined as an input/output port. This input/output port includes a pair of terminals P-0T and P-0B, a pair of terminals P-1T and P-1B, a pair of terminals P-2T and P-2B, and a pair of terminals P-3T and P-3B each corresponding to the bit line pair BP, and transmits data of 4 bits in total. Since a large number of bit lines BL are actually arranged in the memory block 100, a predetermined bit width larger than 4 bits is secured. The input/output port is commonly set for the both sides of the bit lines BL, and is connected through input/output lines (not shown) outside the memory block 100. An internal logic circuit or the like is connected to the input/output port, and multi-bit data can be transferred at high speed between the memory block 100 and the logic circuit.
Meanwhile, it is desirable that the above-mentioned logic circuit mixed DRAM is configured to be capable of being controlled from outside as the same manner in the general DRAM. In this case, it is necessary to provide an input/output port having a narrow bit width corresponding to general DRAM interface so as to be connected to the outside.
FIG. 16 shows a specific example of the DRAM circuit including the input/output port having a narrow bit width. In a memory block 200 as shown in FIG. 16, the basic configuration is common to FIG. 15, but arrangements of the select transistors ST and the input/output port is different from those in FIG. 15. Each bit line is connected to one end of each select transistor ST, and an input/output port is defined via input/output lines in a direction orthogonal to the bit lines BL connected to the other end of each select transistor ST. Further, a column decoder 201 selectively activates four select control lines 202 connected to gates of the select transistors ST each corresponding to a bit line pair BP in response to an input column address. The select control lines 202 of FIG. 16 are arranged approximately in parallel with the bit lines BL, as compared with that the select control lines 102 of FIG. 15 are arranged in a direction orthogonal to the bit lines BL.
In the DRAM circuit of FIG. 16, the above-mentioned input/output port includes a pair of terminals P-0T and P-0B and a pair of terminals P-1T and P-1B, and transmits data of 2 bits in total. In the example of FIG. 16, even when a large number of bit lines BL are arranged in the memory block 200, the bit width is 2 bits. The input/output port is externally connected through the input/output lines outside the memory block 200, and data transfer according to the general DRAM interface can be performed.
However, if the configuration of FIG. 15 is applied to the logic circuit mixed DRAM, for example, mismatch in bit width occurs by commonly using the input/output port having a wide bit width in data transfer to the outside. Thus, an extra control circuit for adjusting different bit widths needs to be provided, and it is a problem that chip area and consumption current increase. Inversely, when the configuration of FIG. 16 is applied to the logic circuit mixed DRAM, it becomes difficult to transfer high capacity data at high speed between the DRAM and the internal logic circuit as shown in FIG. 15.
Meanwhile, a multi port DRAM is conventionally known in which a plurality of input/output ports are added to a memory cell array (see Japanese Patent Laid-Open No. 2003-308690 and Japanese Patent Laid-Open No. 2004-86970). In this case, a configuration can be considered in which a logic circuit mixed DRAM is multi-ported, and two input/output ports connected to the memory cell array are provided to be used separately. However, in the conventional multi port DRAM, it is not assumed that two input/output ports having different use purposes and largely different bit widths are provided, which is difficult in terms of the configuration of the memory cell array and its peripheral circuit. In this manner, when configuring the logic circuit mixed DRAM, it is difficult to use an input/output port having a wide bit width for data transfer to an internal circuit and a general input/output port having a narrow bit width for external data transfer at the same time, and therefore highly efficient data access is not achieved.